A flip-chip bonding technique is an interconnection process for integrating chips onto a substrate. As shown in FIG. 1, carried by a carrying board 5, a plurality of chips 2 on a carrier 1 are bonded to a substrate 4 in batch. The plurality of chips 2 are accurately placed on the carrying board 5 and sucked. During bonding, the chips 2 are securely positioned on the carrying board 5, and the distance L between the chips 2 is accurately maintained. Thus, serial bonding of a single chip 2 is replaced with parallel bonding of a plurality of chips 2, effectively enhancing productivity of the equipment. Moreover, since electronic products develop towards the trend of being light, thin, and miniaturized, the application of the chip bonding technology increases day by day. By combining the chip bonding technique with the wafer-level packaging technique, a package type with a small size and a high performance is able to be produced. If the chip bonding technique and a through-silicon via (TSV) technique are combined, a chip structure with a more competitive cost and performance is able to be produced. At present, there are three fan-out bonding techniques in the field, among which the fan-out bonding technique based on chip First is a widely-applied mainstream process. As shown in FIG. 2a and FIG. 2b, the fan-out bonding technique mainly has two chip mounting manners: the die-up manner (marks on the chips facing upwards) and the die-down manner (marks on the chips facing downwards). The marks 3 on the chips 2 does not contact the substrate 4 in the die-up mounting manner, while the marks 3 on the chips 2 contact the substrate 4 in the die-down mounting manner. The foregoing two mounting manners need different bonding apparatuses for chip bonding, i.e. no universal bonding apparatus is available, thus increasing the production costs.
On the other hand, the bonding technology enables chip stacking and integration to the maximum extent within a limited area without reducing the line width, and can reduce a wafer package size and line conduction length for a system on a chip (SoC), thereby improving wafer transmission efficiency. Compared to the wafer-to-wafer (W2W) technology, the chip-to-wafer (C2W) technology has a higher yield and a lower production cost. Therefore, it is the industry goal to ensure high bonding precision and also maintain high productivity of the C2W technology.